Many computational processes that are performed on digital signal processors (DSPs) require the generation of address values using modulo addition. The basic idea behind modulo addressing is that an address will be incremented or decremented by some Displacement for each new computational cycle until an upper or lower address boundary is reached, at which point the next address will "wrap around" to the other end of the address range being used.
For example, for a specified address range of 100 to 200, with a starting address of 101 and a Displacement of 10, the address value would increment to 111, 121,131, . . . 191 during the next nine computational cycles, and then on the next computational cycle the address would wrap around and be set equal to 101.
The term modulo is defined as follows: EQU Result=A modulo B
means that Result is equal to A if A is less than B, and is equal to the remainder of A divided by B is A is larger than B. Thus, EQU Result=A-A.div.B
where "x" means the integer portion of x.
For "modulo" addressing, each new address is computed as follows: EQU New Address=LowerBoundAddress +(PreviousAddress+Displacement) Modulo Modval
where
LowerBoundAddress is the lower bound on the address range, PA1 PreviousAddress is the address value used in the previous computational cycle, PA1 Modval is the difference between the upper and lower bounds of the address range, and PA1 Displacement is the amount that the address is incremented for each computational cycle.
In a variation on the above modulo addressing example, if the specified address range is made 100 to 199, with the same starting address and Displacement as before, the address value after the wrap around would be set equal to 102. The reason that the new address is equal to 102 instead of 101 is that the new address is computed using the above definition as follows: ##EQU1##
Existing modulo arithmetic implementations on DSP chips have restrictions on the location of the array and on the displacement and address that are to be added. In particular, the location of the array is typically restricted to require that the lower N+1 bits of the array's lower bound address must be equal to 0, where N is the most significant bit of the modulo value set equal to 1. This restriction on the array location is inconvenient because it complicates the problem of optimally locating in memory the various data arrays to be used in a computation. The first preferred embodiment of the present invention avoids this restriction, and thus give users complete flexibility in selecting the location of the memory array to be accessed using modulo addressing.
A second shortcoming in the prior modulo arithmetic implementations on DSPs has been the amount of circuitry required to implement modulo addressing. In particular, prior modulo adder circuits have generally utilized two cascaded adder circuits to generate a new modulo address value every computational cycle.
It is an object of the present invention to provide an address generating circuit that performs modulo addition and is efficient in terms of the amount of circuitry required to implement modulo addition.
Another object of the present invention is to provide a modulo addition address generating circuit that includes a single adder circuit.
Still another object of the present invention is to provide a modulo addition address generating circuit that places no restriction on the range of addresses generated by the modulo addition circuitry.